In general, an image sensor refers to a semiconductor device for converting an optical image into an electrical signal. Image sensors are generally classified as charge coupled device image sensors or CMOS image sensors. A charge coupled device (CCD) image sensor includes metal-oxide-silicon (MOS) capacitors formed very close to each other where charge carriers are stored in and transferred from the capacitors.
A CMOS image sensor is a device employing a switching mode to sequentially detect an output by providing MOS transistors corresponding to the number of pixels, formed using a CMOS technology, in conjunction with peripheral devices, such as a control circuit and a signal processing circuit.
A charge coupled device (CCD) has various disadvantages such as a complicated drive mode and high power consumption. Also, the CCD requires many steps of the mask processes, so the process for the CCD is complicated. In addition, it is difficult to integrate a signal processing circuit onto a single chip of the CCD. Recently, to overcome these disadvantages, CMOS image sensors using a sub-micron CMOS manufacturing technology have been studied and developed.
The CMOS image sensor includes a photodiode and a MOS transistor in each unit pixel to sequentially detect the signal through a switching scheme, thereby realizing the images. Since the CMOS image sensor makes use of the CMOS manufacturing technology, the CMOS image sensor has low power consumption and simplifies the manufacturing process thereof. That is, the CMOS sensor manufacturing process can be achieved by using about 20 masks in contrast with the 30 to 40 masks required by the CCD process. Also, because many signal processors can be integrated onto a single chip of the CMOS image sensor, the CMOS image sensor is spotlighted as a next-generation image sensor. Therefore, the CMOS image sensor is used in various applications such as digital still cameras (DSC), PC cameras, and mobile cameras.
The CMOS image sensors are classified as 3T-type, 4T-type, or 5T-type CMOS image sensors based on the number of transistors formed in a unit pixel. The 3T-type CMOS image sensor includes one photodiode and three transistors, and the 4T-type CMOS image sensor includes one photodiode and four transistors. Hereinafter, description will be made in reference to a layout of a unit pixel of the 3T-type CMOS image sensor.
FIG. 1 is a layout view illustrating the unit pixel of a conventional 3T-type CMOS image sensor.
As shown in FIG. 1, the unit pixel of the 3T-type CMOS image sensor includes one photodiode PD and three transistors.
The three transistors include a reset gate Rx for resetting optical charges collected in the photodiode PD, a drive gate Dx serving as a source follower buffer amplifier, and a select gate Sx performing switching and addressing functions.
Herein, a photodiode area (B) including the photodiode PD is an area in which salicide is not formed, and the area excluding the photodiode area (B), that is, a logic area, is the area in which salicide is formed.
The reason for forming salicide in the logic area is to reduce the resistance, thereby improving the speed of the transistors Rx, Dx and Sx. In addition, salicide is not formed in the photodiode area (B) because salicide reflects light which may interfere with the function of the photodiode PD that reproduces images by receiving the light.
FIG. 2 is a sectional view taken along line A-A′ of FIG. 1, showing the photodiode PD and the reset gate Rx.
As shown in FIG. 2, a reset gate 3 is formed on a semiconductor substrate 1 including a high-density P++ semiconductor substrate and a P-Epi layer with a gate insulating layer 2 interposed therebetween. A photodiode impurity region 4 (hereinafter referred to as “PDN”) is formed in the photodiode area (B) at one side of the reset gate 3.
In addition, an N+ diffusion area 5 is formed in the semiconductor substrate 1 at the other side of the reset gate 3, and insulating layer sidewalls 6 are formed at both sides of the reset gate 3. Further, an LDD area 7 is formed in the semiconductor substrate 1 at the lower part of the insulating layer sidewall 6, and is formed in the vicinity of the N+ diffusion area 5.
As described above, since a salicide layer 8 must not be formed in the photodiode area (B) while being formed only in the logic area, the salicide layer 8 is not formed on the portion of the reset gate 3 formed in the photodiode area (B). The salicide layer 8 is formed on the portion of the reset gate 3 formed in the logic area and on the N+ diffusion area 5. Here, reference numeral 9 is an isolation layer.
FIGS. 3a through 3i are sectional views showing a procedure for manufacturing a conventional CMOS image sensor.
Referring to FIG. 3a, an epitaxial process is performed relative to a semiconductor substrate 100 including high-density first conductive (P++ type) multi-crystalline silicon, thereby forming a low-density first conductive (P− type) epitaxial layer 101.
Here, the epitaxial layer 101 enlarges and deepens a depletion region of the photodiode, thereby increasing the capability and the photo sensitivity of a low-voltage photodiode for collecting optical charges.
Then, an active area and an isolation area are defined on the semiconductor substrate 100, and a STI process or a LOCOS process is performed, thereby forming an isolation layer 102 on the isolation area.
After that, a gate insulating layer 103 and a conductive layer are sequentially deposited on the entire surface of the epitaxial layer 101 having the isolation layer 102. The conductive layer and the gate insulating layer 103 are selectively removed, thereby forming a gate electrode 104 of each transistor.
Then, a first photoresist film 105 is coated on the entire surface of the semiconductor substrate 100 including the gate electrode 104, and then an exposure and development process is performed so as to selectively pattern the first photoresist film 105 such that the photodiode area can be exposed.
Thereafter, low-density N− type dopants are implanted into the exposed photodiode area using the first photoresist film 105 as a mask, thereby forming a PDN area 106.
Referring to FIG. 3b, after completely removing the first photoresist film 105, a second photoresist film 107 is coated on the entire surface of the semiconductor substrate 100, and then an exposure and development process is performed relative to the second photoresist film 107 such that the transistor area can be exposed. Thereafter, low-density N− type dopants are implanted into the epitaxial layer 101 using the second photoresist film 107 as a mask to form an LDD area 108.
Herein, the PDN area 106 is formed deeper than the LDD area 108 because dopants are implanted into the photodiode area with a higher energy to form the PDN area 106.
Referring to FIG. 3c, after completely removing the second photoresist film 107, a TEOS layer 109 having a thickness of about 200 Å is formed on the entire surface of the semiconductor substrate 100, and a nitride layer 110 is formed on the TEOS layer 109.
Referring to FIG. 3d, a nitride layer sidewall 110a is formed at both sides of the gate electrode 104 by performing an etch-back process on the entire surface of the nitride layer 110.
Referring to FIG. 3e, a third photoresist film 111 is coated on the entire surface of the semiconductor substrate 100, and an exposure and development process is performed relative to the third photoresist film 111 such that the third photoresist film 111 remains only on the photodiode area and the isolation layer 102 to expose source/drain areas of the transistors.
Thereafter, high-density N+ type dopants are implanted into the exposed source/drain area by using the third photoresist film 111 as a mask, thereby forming a high-density N+ type diffusion area 112.
Referring to FIG. 3f, after removing the third photoresist film 111, a heat treatment process (e.g., a rapid thermal process of 800° C. or higher) is performed, thereby diffusing the dopants in the N− type diffusion area 106, the low-density N− type diffusion area 108 and the high-density N+ type diffusion area 112.
Then, a silicide blocking layer 113 is formed on the entire surface of the semiconductor substrate 100.
Referring to FIG. 3g, after coating a fourth photoresist film 114 on the silicide blocking layer 113, an exposure and development process is performed relative to the fourth photoresist film 114 such that an area in which silicide will be later formed can be defined.
After that, the exposed part of the silicide blocking layer 113 and the TEOS layer 109 are selectively removed using the fourth photoresist film 114 as a mask such that the surface of the high-density N+ type diffusion area 112 is exposed.
Referring to FIG. 3h, after removing the fourth photoresist film 114 and depositing a refractory metal layer on the entire surface of the semiconductor substrate 100, a heat treatment process is performed, thereby forming a metal silicide layer 115 on the surface of the high-density N+ type diffusion area 112.
Then, a portion of the refractory metal layer, which has not reacted with the semiconductor substrate 100, is removed.
Referring to FIG. 3i, a nitride layer is deposited on the entire surface of the semiconductor substrate 100 so as to form a diffusion blocking nitride layer 116. Then, an interlayer dielectric layer 117 is formed on the diffusion blocking nitride layer 116.
After that, although not shown, power lines, color filter layers, micro lenses, etc. are formed on the interlayer dielectric layer 117, thereby forming a CMOS image sensor.
Currently, a common method for manufacturing the CMOS image sensor employs technology having the scale ranging from 0.35 μm to 0.18 μm.
Moreover, as the chip becomes highly integrated, the development of technology having the scale of 0.18 μm or less has become competitive. Meanwhile, the thermal budget is seriously restricted in the technology having the scale of 0.25 μm or more. This restriction is derived from the use of silicide. After a silicide is formed, a high temperature process (800° C. or more) is restricted from being performed, so it is difficult to remove impurities causing a dark current.
Meanwhile, in the conventional method, the heat treatment process for the LDD area and the photodiode area, and the heat treatment process after source and drain ion implantation can be performed at the temperature of 800° C. or higher so as to recover the damage of a lattice and to activate the process. However, the temperature of a heat treatment process related to the interlayer dielectric layer 117 is restricted.
Thus, in order to form the metal silicide layer 115 and to realize the shallow junction, the heat treatment process is performed at the temperature of 700° C. or less.
The interlayer dielectric layer 117 may include a BPSG-based insulating layer, and as the temperature becomes higher, the gettering effects for impurities regarding the BPSG become more efficient so as to enhance the dark current in the process of manufacturing the image sensor. However, it is difficult to realize such effects through performing the heat treatment process under the above-mentioned temperature.
In addition, before forming the interlayer dielectric layer 117, the diffusion barrier 116 including the nitride layer is formed, so the photodiode area is reduced when scaling down, so that the dynamic range is reduced. As a result, light transmittance decreases, making it difficult to reproduce the images.